//****************************************************************************
//                      RGB_Test
//
//功能：生成测试图像
//
//版本:
//****************************************************************************
module RGB_Test(
		input	wire			resetb,
		input	wire			sclk,
		
		input	wire			cfg_wen,
		input	wire	[11:0]	cfg_waddr,
		input	wire	[7:0]	cfg_wdata,
		
		input	wire			pclk,
		input	wire			vsin1,
		input	wire			hsin1,
		input	wire			dein1,
		input	wire			vsin0,
		input	wire			hsin0,
		input	wire			dein0,
		input	wire	[47:0]	datain,
		
		output	wire			vsout,
		output	wire			hsout,
		output	wire			deout,
		output	wire	[47:0]	dout
		);

//******************************************************************************
//                              参数定义
//******************************************************************************

//******************************************************************************
//                              信号定义
//******************************************************************************
(*keep*)reg		[7:0]	Test_Mode, R_Set_D, G_Set_D, B_Set_D;

reg				vs, hs, de;
reg		[12:0]	i_p_count;
reg		[47:0]	i_ddd;
wire	[7:0]	aaa, bbb;

//******************************************************************************
//                              设置参数
//******************************************************************************
always @(posedge sclk or negedge resetb)
	if (resetb == 0) begin
		Test_Mode		<= 0;
		R_Set_D			<= 0;
		G_Set_D			<= 0;
		B_Set_D			<= 0;
		end
	else if (cfg_wen == 1)
		case (cfg_waddr)
			12'h110:	Test_Mode 	<= cfg_wdata;
			12'h120:	R_Set_D 	<= cfg_wdata;
			12'h122:	G_Set_D 	<= cfg_wdata;
			12'h124:	B_Set_D 	<= cfg_wdata;
		endcase

//******************************************************************************
//                              时序计数
//******************************************************************************
always @ (posedge pclk) begin
	vs <= vsin0;
	hs <= hsin0;
	de <= dein0;
	end
	
always @(posedge pclk)
	if (dein0 == 1)
		i_p_count <= i_p_count + 1;	
	else		
		i_p_count <= 0;	

//******************************************************************************
//                              数据控制
//******************************************************************************
assign	aaa = i_p_count[11:4];
assign	bbb = aaa + 1;

always @(posedge pclk)
	if (dein0 == 0)
		i_ddd <= 0;
	else if (Test_Mode == 0)
		i_ddd <= datain;
	else if (Test_Mode == 1)
		i_ddd <= {2{B_Set_D, G_Set_D, R_Set_D}};
	else
		i_ddd <= {6{aaa}};

//******************************************************************************
//                              输出信号
//******************************************************************************
assign	vsout	= vs;
assign	hsout	= hs;
assign	deout	= de;
assign	dout	= i_ddd;

endmodule